1. Technical Field
This disclosure relates to processors, and more particularly to speculative predicated vector instruction execution.
2. Description of the Related Art
To improve performance, many out-of-order execution processors look ahead into the program to gather instructions. In many cases, as soon as the input parameters are available, the instruction is executed. Depending on the type of instruction the earlier the instruction can be issued, the better the performance of the processor. For example, memory read operations may have a long latency due to the performance of the memory that is being read. Thus, as soon as the memory address is generated, the memory read operation may be issued. In addition, some arithmetic operations such as divide instructions, for example, may have long latencies due to the number of pipeline stages used in the instruction execution. Thus, instructions like the divide instruction may be issued as soon as the operands are available.
However, some conventional processors that process vector instructions use predication when performing calculations to control whether individual elements of a vector are modified. Accordingly, in a conventional processor, when an instruction depends on a predicate vector, that instruction must wait for the predicate to become available before the instruction is executed. The latencies associated with this type of waiting may be inefficient and may adversely affect performance.